1. Technical Field of the Invention
This invention relates generally to integrated circuits and more particularly to design, layout, and fabrication of high-density integrated circuits.
2. Description of Related Art
As is known, the traditional design flow of an integrated circuit (IC) includes: (1) establishing architectural and electrical specifications; (2) RTL (Register Transfer Level) coding; (3) RTL simulation; (4) synthesis of the RTL code to produce a netlist; (5) formal verification; (6) pre-layout chip level static timing verification; (7) place and global routing; (8) formal verification; (9) post global routing static timing verification; (10) detailed routing; (11) post-layout testing; and (12) tape out. In such a design process, the architectural specification provides functional partitioning of the IC into manageable blocks (e.g., defines the die area and which areas of the die will support memory, digital circuitry, input/output circuitry, analog circuitry, etc.). The electrical specification provides the timing relationship between the blocks and the electrical function of the blocks (e.g., the analog block includes analog to digital converters, amplifiers, drivers, etc., and at what speeds data is to be conveyed).
From the architectural and electrical specifications, RTL code is generated to describe the functionality of the blocks and/or circuits within the blocks. As is known, the RTL code may be hierarchically arranged to connect top-level blocks with lower level blocks. Once the RTL code is generated, it is simulated to verify that the design functionally meets the electrical specifications. Note that gate timing is not tested at this step of the IC design process. If the design fails the simulation, the design is modified, new RTL code is produced, and subsequently resimulated.
Once the design passes the simulation, a design compiler generates a netlist based on the RTL code, a cell library, and environmental and timing constraints. With the netlist generated, the design is formally verified to test the logical functioning of the IC design. In general, the formal verification at this phase of the IC design is to validate RTL against RTL, gate-level netlist against the RTL code, and/or a comparison between gate-level netlists.
The IC design process then proceeds to the pre-layout chip level static timing verification step, which determines net delays within the IC and compares them with the timing constraints. If the net delays are less than the timing constraints, the IC design process continues with the place and global routing step. If, however, the net delays are greater than the timing constraints, the process reverts to the synthesis step to generate a new netlist. Note that the static timing verification may focus only on the critical paths within the IC to reduce testing time.
During the place and global routing step, the gates of the circuits of the blocks are placed in the layout of the IC. Many commercially available place and route algorithms employ a time driven placement method that places cells (i.e., a gate or series of gates) in the layout based on critical timing between the cells. Once the cells are places, the clock circuitry and lines (e.g., a clock tree) are inserted into the layout. Next, global routing is performed to determine the quality of the placement and to provide estimated delays.
At this point in the IC design process, the IC is again formally tested to determine whether the net delays are less than the timing constraints. If so, the IC design process continues by performing another static timing verification. If not, the place and global routing step is repeated. If the static timing verification produces acceptable timing, the process continues by performing detailed routing. If, however, the timing is not acceptable, the IC design process reverts to the RTL synthesis step to generate a new netlist.
During the detailed routing step, the gates are coupled together via the place and route tool. Once this step is completed, the initial IC layout is finished. Before taping out and subsequently fabrication first silicon (i.e., a prototype IC), the IC layout is tested for timing violations, antenna violations (i.e., metal traces that are subject to accumulate a charge that could potentially damage the gate oxide layer of a transistor), adverse parasitic affects, etc.
If an antenna violation is detected, the place and route tools resolve the violation by first attempting to place a diode in the immediate proximity of the affected device. If a diode can be placed, it is then attached in a reverse manner to the affected device. As an alternate method for resolving an antenna violation, the place and route tool may place the affected trace on multiple metal layers and connect the trace segments with vias. In high-density integrated circuit layouts, these methods are generally not able to solve antenna violations, since there is typically very little unused die area, making it, at times, impossible to place a diode near the affected device or to place the affected trace on multiple layers. As such, with conventional place and rout tools, the IC design fails due to the uncorrectable antenna violations, which requires a substantial redesign effort to manually resolve the antenna violations.
Therefore, a need exists for a method that resolves antenna violations in high-density integrated circuit layouts without the need for a substantial IC redesign.